A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW

Calibration of DAC mismatch errors in sigma delta ADCs based on a sine-wave measurement

We present an offline calibration procedure to correct the nonlinearity due element mismatch in the digital-to-analog converter (DAC) of a multibit Sigma Delta-modulation A/D converter. The calibration uses a single measurement on a sinusoidal input signal, from which the DAC errors can be estimated. The main quality of the calibration method is that it can be implemented completely in the digital domain (or in software) and does not intervene in any way in the analog modulator circuit. This way, the technique is a powerful tool for verifying and debugging designs. Due to the simplicity of the method, it may be also a viable approach for factory calibration

ToViLaG: Your Visual-Language Generative Model is Also An Evildoer

Warning: this paper includes model outputs showing offensive content. Recent large-scale Visual-Language Generative Models (VLGMs) have achieved unprecedented improvement in multimodal image/text generation. However, these models might also generate toxic content, e.g., offensive text and pornography images, raising significant ethical risks. Despite exhaustive studies on toxic degeneration of language models, this problem remains largely unexplored within the context of visual-language generation. This work delves into the propensity for toxicity generation and susceptibility to toxic data across various VLGMs. For this purpose, we built ToViLaG, a dataset comprising 32K co-toxic/mono-toxic text-image pairs and 1K innocuous but evocative text that tends to stimulate toxicity. Furthermore, we propose WInToRe, a novel toxicity metric tailored to visual-language generation, which theoretically reflects different aspects of toxicity considering both input and output. On such a basis, we benchmarked the toxicity of a diverse spectrum of VLGMs and discovered that some models do more evil than expected while some are more vulnerable to infection, underscoring the necessity of VLGMs detoxification. Therefore, we develop an innovative bottleneck-based detoxification method. Our method could reduce toxicity while maintaining comparable generation quality, providing a promising initial solution to this line of research.Comment: Accepted by EMNLP 2023 (Main Conference), Oral Presentatio

Design of High-Bandwidth Low-Power Delta-Sigma Modulators (Ontwerp van delta-sigma modulatoren met hoge bandbreedte en laag vermogenverbruik)

This work focuses on the design of high-bandwidth low-power DSM ADCs, both at architecture level and circuit level. The first two designs are 40MHz-bandwidth 12-bit CT DSMs implemented in 90nm CMOS. The quantizations are done by the highly-digital phase-type VCO-based quantizer with 1st-order noise shaping. In the first design, the shaped switched-capacitor digital-to-analog converter (SC DAC) is proposed to relax the amplifier slew-rate requirement, and the look-up-table (LUT)-based digital calibration is presented to eliminate the distortion of the multi-bit SC DAC. With 960MHz sampling frequency and 69.6mW power, the DSM achieves 72.9dB SNDR. The second design is an improved design, where several techniques are applied to target lower power: a half-period delay instead of a full-period delay is assigned for the feedback to tolerate a larger phase shift in the loop filter; the current-sharing OTA is applied to reduce the power consumption in the analog integrators. The DSM reaches 69.7dB SNDR, with a power consumption of 45mW.This work also proposes a two-step open-loop VCO-based ADC architecture, which is a robust hardware-economic structure with an excellent figure-of-merit (FoM). The VCO-based quantizer nonlinearities are mitigated by distortion cancellation and input-swing reduction techniques. Because of the intrinsic DEM on the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. Measurements of a 40nm CMOS demonstration show that the ADC achieves 59.5dB SNDR for a 40MHz signal bandwidth, with 1.6GHz sampling frequency and only 2.57mW power consumption, corresponding to an excellent FoM of 42fJ/Step.With state-of-the-art power efficiencies, the presented high-bandwidth ADCs are very suitable for application in next-generation communication standards, including VDSL2+, 802.11n and LTE.Acknowledgement i Abstract iii List of Abbreviations and Symbols v Contents ix List of Figures xiii List of Tables xix 1 Introduction 1 1.1 Background and motivation . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Communication evolution . . . . . . . . . . . . . . . . . . 1 1.1.2 CMOS technology . . . . . . . . . . . . . . . . . . . . . 4 1.1.3 Receiver architectures . . . . . . . . . . . . . . . . . . . 7 1.2 The research objective and major contributions of the thesis . . 9 1.3 The thesis organization . . . . . . . . . . . . . . . . . . . . . . 10 2 A/D Converters and Their Applications 13 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ix x CONTENTS 2.2 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 ADC speed . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 ADC FoM . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 ADC architectures . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.2 Two-Step ADC . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.3 Pipelined ADC . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.4 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3.5 Delta-Sigma ADC . . . . . . . . . . . . . . . . . . . . . 27 2.3.6 ADC architecture summmary and comparison . . . . . . 29 2.4 Application of ADC in communications . . . . . . . . . . . . 30 2.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3 Continuous-Time Delta-Sigma Modulators 39 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.2 DSM basics: oversampling and noise-shaping . . . . . . . . . . 40 3.3 DSM structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.3.1 Discete-time and continuous-time DSMs . . . . . . . . . 43 3.3.2 1st-order and higher-order DSMs . . . . . . . . . . . . . 47 3.3.3 Single-loop and MASH DSMs . . . . . . . . . . . . . . . 49 3.3.4 Single-bit and multi-bit DSMs . . . . . . . . . . . . . . . 51 3.3.5 Feedforward, feedback and hybrid DSMs . . . . . . . . . 55 3.3.6 Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.7 Feedin paths . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 CT DSM nonidealities and modeling . . . . . . . . . . . . . . . 57 3.4.1 Loop filter nonidealities and modeling . . . . . . . . . . 57 CONTENTS xi 3.4.2 DAC nonidealities and modelling . . . . . . . . . . . . . 63 3.4.3 Quantizer nonidealities and modeling . . . . . . . . . . 68 3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 VCO-Based ADCs 71 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 VCO-based quantizers . . . . . . . . . . . . . . . . . . . . . . . 72 4.2.1 Single-phase counting VCO-based quantizer . . . . . . . 72 4.2.2 Multi-phase counting VCO-based quantizer . . . . . . . 73 4.2.3 Frequency-type VCO-based quantizer . . . . . . . . . . 74 4.2.4 Phase-type VCO-based quantizer . . . . . . . . . . . . . 76 4.3 Closed-loop VCO-based DSMs . . . . . . . . . . . . . . . . . . 77 4.3.1 DSM with frequency-type VCO-based quantizer . . . . 78 4.3.2 DSM with phase-type VCO-based quantizer . . . . . . . 79 4.3.3 DSM with residual-cancelling VCO-based quantizer . . 80 4.4 Open-loop VCO-based ADCs . . . . . . . . . . . . . . . . . . . . 81 4.4.1 VCO-based ADC with background digital calibration . . 81 4.4.2 VCO-based ADC with counting and foreground digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.4.3 VCO-based ADC with PWM precoding . . . . . . . . . 84 4.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5 40MHz-BW 12-bit Low-Power CT DSMs in 90nm CMOS 87 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2 A 40MHz-BW 12-bit CT DSM with digital calibration and shaped SC DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.1 Structure of the CT DSM . . . . . . . . . . . . . . . . . 89 5.2.2 Delta-Sigma modulator building blocks design . . . . . . 94 xii CONTENTS 5.2.3 Measurement setup and experimental results . . . . . . . 101 5.3 A 40MHz-BW 12-bit CT DSM with capacitive local feedback and current-sharing OTA . . . . . . . . . . . . . . . . . . . . . 104 5.3.1 System design of the 40MHz 12-bit CT DSM . . . . . . 106 5.3.2 Circuit design of the DSM building blocks . . . . . . . . 108 5.3.3 Measurement results and discussions . . . . . . . . . . . . 111 5.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6 A 40MHz-BW Two-step Open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS 115 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2 Architecture design of two-step open-loop VCO-based ADC . . 116 6.2.1 A two-step open-loop VCO-based ADC architecture . . 117 6.2.2 Nonidealities of the two-step open-loop VCO-based ADC 119 6.3 Circuit implementation of the two-step open-loop VCO-based ADC123 6.3.1 VCO-based quantizer design . . . . . . . . . . . . . . . 124 6.3.2 DAC and subtractor design . . . . . . . . . . . . . . . . 125 6.4 Experimental results and discussions . . . . . . . . . . . . . . . 129 6.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7 Conclusions 137 7.1 Summary and conclusions . . . . . . . . . . . . . . . . . . . . . 137 7.2 Suggestions for future work . . . . . . . . . . . . . . . . . . . . 139 Bibliography 141 List of Publications 151nrpages: 152status: publishe

A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS

A 4th-order 40MHz Bandwidth 12bit continuous-time delta-sigma modulator is presented in this paper. A shaped SC DAC with reduced peak current is proposed to relax the OTA slewing requirement, consuming no extra hardware or power. The DAC static and dynamic mismatches are eliminated by lookup table based digital calibration. With 1.2V supply and 69.6mW power in 90nm CMOS, the modulator achieves excellent SFDR of 84.2dB and 72.9dB peak SNDR at 960MHz clock frequency, corresponding to a FoM of 0.24pJ/Step. The core circuit area is about 0.28mm2

The Relationship between Green Organization Identity and Corporate Environmental Performance: The Mediating Role of Sustainability Exploration and Exploitation Innovation

The link between green organizational identity (GOI) and corporate environmental performance (CEP) has been investigated, but existing studies have no consistent conclusion. A significant research gap remains regarding the mediating role of sustainability exploration innovation (SER), sustainability exploitation innovation (SEI), and the moderating role of government environmental regulation (GER). This study explored the relationship between GOI and CEP in a moderated meditation model which includes SER, SEI, and GER. Using structural equation modelling and bootstrap method based on data sets from of 380 Chinese companies, the results show that: (1) GOI promotes SER, thereby enhancing CEP; (2) GOI promotes SEI, thereby enhancing CEP; (3) GER can positively moderate the indirect effect of GOI on CEP via SER; (4) GER negatively moderate the indirect effect of GOI on CEP via SEI. These findings suggest that firms choose different innovative ways between SER and SEI to improve CEP which depends on different levels of GER in China

A Wireless High-Sensitivity Fetal Heart Sound Monitoring System

In certain cases, the condition of the fetus can be revealed by the fetal heart sound. However, when the sound is detected, it is mixed with noise from the external environment as well as internal disturbances. Our exclusive sensor, which was constructed of copper with an enclosed cavity, was designed to prevent external noise. In the sensor, a polyvinylidene fluoride (PVDF) piezoelectric film, with a frequency range covering that of the fetal heart sound, was adopted to convert the sound into an electrical signal. The adaptive support vector regression (SVR) algorithm was proposed to reduce internal disturbance. The weighted-index average algorithm with deviation correction was proposed to calculate the fetal heart rate. The fetal heart sound data were weighted automatically in the window and the weight was modified with an exponent between windows. The experiments show that the adaptive SVR algorithm was superior to empirical mode decomposition (EMD), the self-adaptive least square method (LSM), and wavelet transform. The weighted-index average algorithm weakens fetal heart rate jumps and the results are consistent with reality